Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer

ABSTRACT

Embodiments of a silicon-on-insulator (SOI) wafer having an etch stop layer overlying the buried oxide layer, as well as embodiments of a method of making the same, are disclosed. The etch stop layer may comprise silicon nitride, nitrogen-doped silicon dioxide, or silicon oxynitride, as well as some combination of these materials. Other embodiments are described and claimed.

FIELD OF THE INVENTION

The invention relates generally to the manufacture of integrated circuitdevices and, more particularly, to the manufacture of asilicon-on-insulator (SOI) wafer having an etch stop layer overlying theburied oxide layer.

BACKGROUND OF THE INVENTION

A silicon-on-insulator (SOI) wafer may include a base layer of silicon,an insulating layer comprised of silicon dioxide overlying the baselayer, and an upper silicon layer overlying the silicon dioxide layer.The silicon dioxide insulating layer is often referred to as the “buriedoxide” layer. Integrated circuits including a collection of transistorsand other circuit elements can be fabricated in the upper silicon layer.SOI wafers offer the potential for fabricating large-scale integratedcircuits (ICs) that, for example, provide high-speed operation andexhibit low power consumption.

Methods for manufacturing SOI wafers include wafer bonding andseparation by implanted oxygen (SIMOX). To form an SOI wafer by waferbonding, a silicon dioxide layer is formed on one surface of a firstsilicon wafer, and a second silicon wafer is then bonded to this surface(e.g., the surface over which the oxide layer has been formed). Thesecond wafer, which may be thinned, forms an upper silicon layer thatoverlies a buried oxide layer. To form an SOI wafer by SIMOX, oxygenions are implanted into a silicon wafer, and the wafer is annealed toform a buried layer of silicon dioxide within the silicon wafer. Anexample of a SIMOX process can be found in Matsumura et al.,Technological Innovation in Low-Dose SIMOX Wafers Fabricated by anInternal Thermal Oxidation (ITOX) Process, MICROELECTRONIC ENGINEERING,Vol. 66, pgs. 400-414 (2003).

One problem with SOI wafers is that the buried oxide layer may providepoor etch resistance (during, for example, the formation of isolationtrenches). It has been suggested that silicon nitride be used as theinsulating layer in an SOI wafer rather than silicon dioxide, as siliconnitride may in some instances provide better etch resistance thansilicon dioxide. An example of a technique for creating an SOI waferhaving a silicon nitride insulating layer is described in Meekison etal., A Transmission Electron Microscope Investigation of the DoseDependence of the Microstructure of Silicon-on-Insulator StructuresFormed by Nitrogen Implantation of Silicon, JOURNAL OF APPLIED PHYSICS,Vol. 69, no. 6 (1991). Silicon nitride is, however, a poor insulator incomparison to silicon dioxide. The band gap of silicon nitride isapproximately 40 percent less than that of silicon dioxide, so theelectrical isolation afforded by silicon nitride is significantly lessthan that provided by silicon dioxide.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view of one embodiment of an SOI wafer having an etchstop layer overlying a buried oxide layer.

FIG. 1B is a cross-sectional elevation view of the SOI wafer of FIG. 1A,as taken along line B-B of FIG. 1A.

FIG. 2 is a block diagram illustrating an embodiment of a method ofcreating an etch stop layer in a SOI wafer.

FIGS. 3A-3C are schematic diagrams illustrating embodiments of themethod shown in FIG. 2.

FIG. 4 is a schematic diagram showing nitrogen concentration vs. waferdepth for various embodiments of the method illustrated in FIG. 2.

FIG. 5 is a block diagram illustrating an embodiment of a method ofcreating an SOI wafer having an etch stop layer overlying the buriedoxide.

FIGS. 6A-6D are schematic diagrams illustrating embodiments of themethod shown in FIG. 5.

FIG. 7 is a schematic diagram showing both nitrogen concentration andoxygen concentration vs. wafer depth for various embodiments of themethod illustrated in FIG. 5.

FIG. 8 is a schematic diagram illustrating an embodiment of a computersystem, which may include a semiconductor die formed according to thedisclosed embodiments.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of a method for fabricating a silicon-on-insulator (SOI)wafer having an etch stop layer overlying the insulating layer aredisclosed. Also disclosed are embodiments of an SOI wafer having an etchstop layer overlying the insulating layer, wherein the insulating layermay comprise silicon dioxide (SiO₂). In one embodiment, the etch stoplayer comprises silicon nitride (Si₃N₄). In another embodiment, the etchstop layer comprises nitrogen-doped silicon dioxide. In a furtherembodiment, the etch stop layer comprises silicon oxynitride(Si_((X))O_((Y))N_((Z))). In yet a further embodiment, the etch stoplayer comprises a combination of two or more of silicon nitride,nitrogen-doped silicon dioxide, and silicon oxynitride. In anotherembodiment, the concentration of nitrogen varies through the thicknessof the etch stop layer (and, perhaps, within other layers of the SOIwafer). The disclosed SOI wafer may provide both the electricalisolation characteristics of an oxide insulating layer and the etch stopcapabilities of the etch stop layer.

Illustrated in FIGS. 1A and 1B is an embodiment of an SOI wafer 100having an etch stop layer overlying an insulating layer. Referring tothese figures, the SOI wafer 100 comprises a base layer of asemiconductor material 110, a layer of an insulating material 120overlying the base layer 110, an etch stop layer 130 overlying theinsulating layer 120, and an upper layer 140 of the semiconductormaterial overlying the etch stop layer 130. In one embodiment, thesemiconductor material (of base layer 110 and upper layer 140) comprisessilicon, and the insulating layer 120 comprises silicon dioxide (SiO₂).In one embodiment, the etch stop layer 130 comprises silicon nitride(Si₃N₄). However, the etch stop layer 130 may not comprise a distinctstoichiometric silicon nitride material, and in other embodiments theconcentration of nitrogen varies through the thickness of the etch stoplayer (and the nitrogen concentration may also vary within other layersof the SOI wafer 100). Thus, for example, in another embodiment the etchstop layer comprises nitrogen-doped silicon dioxide, and in a furtherembodiment the etch stop layer comprises silicon oxynitride(Si_((X))O_((Y))N_((Z))). In yet a further embodiment, the etch stoplayer comprises a combination of two or more of silicon nitride,nitrogen-doped silicon dioxide, and silicon oxynitride.

In one embodiment, the insulating layer 120 has a thickness of betweenapproximately 300-2500 Angstroms, the etch stop layer 130 has athickness of between approximately 3-200 Angstroms, and the uppersemiconductor layer 140 has a thickness of between approximately 30-2000Angstroms. The overall thickness of the SOI wafer 100 is, in oneembodiment, approximately 775 μm for a 300 mm wafer. In a furtherembodiment, the etch stop layer 130 overlies substantially all (or asubstantial portion) of the insulating layer 120, and in a furtherembodiment the upper semiconductor layer 140 overlies substantially all(or a substantial portion) of the etch stop layer 130.

In other embodiments, the base semiconductor layer 110, insulating layer120, etch stop layer 130, and upper semiconductor layer 140 comprisematerials other than those described above. For example, in otherembodiments, an etch stop layer may be formed by doping or implantationof a substance other than nitrogen. Thus, it should be understood thatthe disclosed embodiments are not limited to an etch stop layerincluding nitrogen and, further, that other etch stop materials arewithin the scope of the disclosed embodiments. Furthermore, it should beunderstood that the disclosed etch stop layer may perform otherfunctions in addition to (or in lieu of) that of an etch stop. Forexample, the disclosed nitrogen-containing layer overlying the buriedoxide layer may also function as a diffusion barrier (e.g., as a dopantdiffusion barrier to facilitate doping of the upper semiconductor layer140).

In another embodiment, as shown in FIG. 1A, integrated circuitry for anumber of die 102 may be formed on the SOI wafer 100. The integratedcircuitry of each die 102 may be formed in the upper semiconductor layer140, and the underlying layer 130 may function as an etch stop duringthe formation of this circuitry (e.g., as an etch stop during theformation of isolation trenches, etc.). Although not shown in thefigures for ease of illustration, a number of layers of metallization(each layer of metallization separated from adjacent layers by adielectric layer) may be formed over the wafer 100 to create aninterconnect structure for each die 102. Ultimately, each of the die 102may be singulated from the wafer 100, and each die 102 may be packagedin some manner for integration into a next-level assembly (e.g., acircuit board, a computer system, a wireless communication device,etc.).

The disclosed embodiments encompass various methods of forming an etchstop layer that overlies the buried oxide layer (or other insulatinglayer) of a SOI wafer. Illustrated in FIG. 2 is one embodiment of amethod 200 of forming an etch stop layer in a SOI wafer. Embodiments ofthe method 200 shown in FIG. 2 are further illustrated in the schematicdiagrams of FIGS. 3A through 3C, as well as FIG. 4, and reference shouldbe made to these figures as called out in the text.

Referring first to FIG. 3A, an embodiment of a SOI wafer 300 is shown.This wafer 300 includes a base layer of silicon 310, a layer of silicondioxide 320 overlying the base layer 310, and an upper layer of silicon340. The SOI wafer 300 of FIG. 3A may be formed by any suitable process,such as, for example, wafer bonding or SIMOX.

As set forth in block 210 of FIG. 2, nitrogen is implanted into a SOIwafer. This is illustrated in FIG. 3B, where nitrogen has been implantedinto a region 390 of the SOI wafer 300 of FIG. 3A. It should beunderstood that region 390 is representative of a region that can betargeted for implantation of nitrogen and that, in practice, nitrogenmay be implanted into additional portions of the wafer 300. For example,as will be described below, the nitrogen concentration may vary from asmall amount near the surface of the upper silicon layer 340 to amaximum concentration lower in the wafer, and again vary to a smallamount even deeper into the wafer. The maximum concentration may, forexample, occur at the interface between the upper silicon layer 340 andthe silicon dioxide layer 320, or the maximum nitrogen concentration mayoccur at some point within the silicon dioxide layer 320.

Nitrogen can be implanted under any suitable conditions using anysuitable implantation equipment. In one embodiment, nitrogenimplantation is performed at an elevated temperature to increase thenitrogen concentration while decreasing the potential for damage in theupper silicon layer 340. For example, according to one embodiment,nitrogen implantation is performed at a temperature in a range up to 450degrees Celsius.

The implanted nitrogen will be used to form an etch stop layer, as willbe described below. According to some embodiments, this etch stop layermay comprise silicon nitride, nitrogen-doped silicon dioxide, or siliconoxynitride (or a combination of these materials). Two factors which mayimpact the characteristics of this etch stop layer include the maximumnitrogen concentration and the region or depth that is targeted toreceive the maximum nitrogen dose. This is further illustrated in FIG.4, which shows nitrogen concentration as a function of wafer depth.According to one embodiment, the maximum concentration of nitrogen isimplanted at the interface between the buried oxide layer and the uppersilicon layer. This is illustrated by curve 490 a, which has a maximumnitrogen concentration at the interface between a buried oxide layer 420and an upper silicon layer 440. In another embodiment, the maximumconcentration of the nitrogen is implanted within the buried oxidelayer. This is illustrated by curve 490 b, which has a maximum nitrogenconcentration at some location within the silicon dioxide layer 420. Inone embodiment, the maximum concentration of nitrogen may be within arange up to 10²⁰ atoms/cm³.

Targeting the maximum nitrogen concentration at the interface betweenthe buried oxide layer and the upper silicon layer may provide thegreatest thickness of silicon nitride above the buried oxide layer,whereas targeting the maximum nitrogen concentration at a region withinthe buried oxide layer may reduce the concentration of nitrogen in theupper silicon layer. The maximum nitrogen concentration and the regiontargeted to receive the maximum concentration will be a function of thedesired characteristics of the SOI wafer, and these variables—as well asothers, such as the implantation conditions—can be tailored asappropriate on a case-by-case basis.

It should be noted that, in FIG. 4, the curves 490 a, 490 b representingthe nitrogen concentration as a function of depth have been idealizedfor ease of illustration and understanding. For example, the curves 490a, 490 b are shown as being generally smooth and continuous; however, inpractice, there may be discontinuities in nitrogen concentration at theboundaries between material layers.

Referring next to block 220 in FIG. 2, an annealing process is performedto form an etch stop layer. This is illustrated in FIG. 3C, where anetch stop layer 330 has been formed in the SOI wafer 300, this etch stoplayer disposed above the buried oxide layer 320 and below the uppersilicon layer 340. According to one embodiment, while at elevatedtemperature during anneal, silicon nitride precipitates begin to form,and these precipitates will gather nitrogen from the surroundingsilicon. Thus, as heating continues, diffusion and/or redistribution ofnitrogen may occur and a silicon nitride layer may form at the interfacebetween the upper silicon layer 340 and the buried oxide layer 320.

As previously noted, however, the etch stop layer may not comprise adistinct stoichiometric silicon nitride layer, and the formation ofsilicon nitride precipitates may not occur. Further, in otherembodiments, the nitrogen concentration of the formed etch stop layermay vary continuously through the interface region between the uppersilicon layer and the buried oxide layer. For example, the maximumconcentration of nitrogen in the etch stop layer may occur at theinterface region between the upper silicon layer and the buried oxidelayer, with the nitrogen concentration decaying away into the buriedoxide layer (as well as decaying into the upper silicon layer).Accordingly, in one embodiment, the etch stop layer 330 may comprisenitrogen-doped silicon dioxide, and in a further embodiment the etchstop layer may comprise silicon oxynitride. In another embodiment, theetch stop layer 330 may comprise a combination of two or more of siliconnitride, nitrogen-doped silicon dioxide, and silicon oxynitride.

Annealing to form the etch stop layer (from the implanted nitrogen) maybe performed under any suitable conditions which can lead to theformation of silicon nitride, nitrogen-doped silicon dioxide, or siliconoxynitride (or some combination of these materials). In one embodiment,anneal is performed at a temperature of approximately 1200 degreesCelsius for approximately 2 hours. According to another embodiment, theSOI wafer is placed in a process chamber in which nitrogen can beintroduced, and annealing is performed in a flowing nitrogenenvironment.

Illustrated in FIG. 5 is another embodiment of a method 500 of forming aSOI wafer including an etch stop layer. Embodiments of the method 500shown in FIG. 5 are further illustrated in the schematic diagrams ofFIGS. 6A through 6D, as well as FIG. 7, and reference should be made tothese figures as called out in the text.

Referring first to FIG. 6A, an embodiment of a wafer 600 is shown. Inone embodiment, the wafer 600 includes a substrate 605 comprised ofsilicon.

As set forth in block 510 of FIG. 5, oxygen is implanted into a siliconwafer. This is illustrated in FIG. 6B, where oxygen has been implantedinto a region 680 of the wafer 600 of FIG. 6A. The implanted oxygen willbe used to form a buried oxide layer. It should be understood that theregion 680 is representative of a region that can be targeted forimplantation of oxygen and that, in practice, oxygen may be implantedinto additional portions of the wafer 600. By way of example, the oxygenconcentration may vary from a small amount near the upper surface of thewafer 600 to a maximum concentration lower in the wafer, and again varyto a small amount even deeper into the wafer.

Oxygen can be implanted under any suitable conditions using any suitableimplantation equipment. According to one embodiment, oxygen is implantedat an elevated temperature to increase the oxygen concentration whiledecreasing the potential for damage in the silicon substrate 605. By wayof example, in one embodiment, oxygen implantation is performed at atemperature in a range up to 450 degrees Celsius. The maximum oxygenconcentration is targeted at that region or depth of the wafer where theburied oxide layer is to be formed. This is illustrated in FIG. 7, whichshows the oxygen concentration as a function of wafer depth (nitrogenconcentration is also shown in this figure and will be described below).The curve 780 (dashed line) represents the oxygen concentration, andthis curve suggests that the maximum oxygen concentration falls withinthat region of the wafer where a buried oxide layer (see item 720) is tobe formed. In one embodiment, the maximum oxygen concentration may bewithin a range up to 10²² atoms/cm³.

Referring to block 520 in FIG. 5, nitrogen is implanted into the wafer.This is illustrated in FIG. 6C, where nitrogen has been implanted into aregion 690 of the silicon wafer 600. It should be understood that region690 is representative of a region that can be targeted for implantationof nitrogen and that, in practice, nitrogen may be implanted intoadditional portions of the wafer 600. For example, as will be describedbelow, the nitrogen concentration may vary from a small amount near theupper surface of the wafer 600 to a maximum concentration lower in thewafer, and again vary to a small amount even deeper into the wafer. Themaximum concentration may, for example, occur at that region that is tobecome the interface between an upper silicon layer and a buried oxidelayer, or the maximum nitrogen concentration may occur at some pointwithin that region that is to become the buried oxide layer.

As before, nitrogen can be implanted under any suitable conditions usingany suitable implantation equipment. In one embodiment, nitrogenimplantation is performed at an elevated temperature to increase thenitrogen concentration while decreasing the potential for damage to thewafer 600 (e.g., that portion of wafer 600 that is to become an uppersilicon layer 640). For example, according to one embodiment, nitrogenimplantation is performed at a temperature in a range up to 450 degreesCelsius.

The implanted nitrogen will be used to form an etch stop layer thatoverlies the buried oxide layer (that is to be formed from the implantedoxygen). In some embodiments, this etch stop layer may comprise siliconnitride, nitrogen-doped silicon dioxide, or silicon oxynitride (or acombination of these materials). As noted above, two factors which mayimpact the characteristics of the silicon nitride layer include themaximum nitrogen concentration and the region or depth that is targetedto receive the maximum nitrogen dose. This is illustrated in FIG. 7,which shows nitrogen concentration (and oxygen concentration) as afunction of wafer depth. According to one embodiment, the maximumconcentration of nitrogen is implanted at that region that is to becomethe interface between a buried oxide layer and an upper silicon layer.This is illustrated by curve 790 a, which has a maximum nitrogenconcentration at that plane that is to become the interface between asilicon dioxide layer 720 and an upper silicon layer 740. In anotherembodiment, the maximum concentration of nitrogen is implanted within aregion that is to become a buried oxide layer. This is illustrated bycurve 790 b, which has a maximum nitrogen concentration at some locationwithin the region that is to become the buried oxide layer 720. In oneembodiment, the maximum concentration of nitrogen may be within a rangeup to 10²⁰ atoms/cm³.

Targeting the maximum nitrogen concentration to be at the interfacebetween the buried oxide layer and the upper silicon layer may providethe greatest thickness of silicon nitride above the buried oxide layer,whereas targeting the maximum nitrogen concentration to be at a regionwithin the buried oxide layer may reduce the concentration of nitrogenin the upper silicon layer. As previously suggested, the maximumnitrogen concentration (and maximum oxygen concentration) and the regiontargeted to receive the maximum concentration will be a function of thedesired characteristics of the SOI wafer, and these variables—as well asothers, such as the implantation conditions—can be tailored asappropriate on a case-by-case basis.

It should be noted that, in FIG. 7, the curves 790 a, 790 b representingthe nitrogen concentration as a function of depth (as well as curve 780representing the oxygen concentration) have been idealized for ease ofillustration and understanding. For example, the curves 790 a, 790 b(and 780) are shown as being generally smooth and continuous; however,in practice, there may be discontinuities in nitrogen concentration atthe boundaries between material layers.

As set forth in block 530 in FIG. 5, an annealing process is performedto form a silicon dioxide layer as well as an etch stop layer. This isillustrated in FIG. 6D, where a silicon dioxide layer 620 and an etchstop layer 630 have each been formed to create a SOI wafer 600. Thesilicon dioxide layer 620 is formed in that region of the silicon waferthat was targeted for oxygen implantation, and the etch stop layer 630is formed in the interface region between the silicon dioxide layer 620and an upper silicon layer 640. Thus, the etch stop layer is disposedabove the buried oxide layer 620 and below the upper silicon layer 640.According to one embodiment, during anneal at elevated temperature,silicon nitride precipitates begin to form, and these precipitates willgather nitrogen from the surrounding silicon. Thus, as heatingcontinues, diffusion and/or redistribution of nitrogen will occur and asilicon nitride layer may form at the interface between the uppersilicon layer 640 and the buried oxide layer 620 that is forming.Similar mechanisms may lead to the formation of the silicon dioxidelayer.

As previously noted, however, the etch stop layer may not comprise adistinct stoichiometric silicon nitride layer, and the formation ofsilicon nitride precipitates may not occur. Further, in otherembodiments, the nitrogen concentration of the formed etch stop layermay vary continuously through the interface region between the uppersilicon layer and the buried oxide layer that is forming. For example,the maximum concentration of nitrogen in the etch stop layer may occurat the interface region between the upper silicon layer and the buriedoxide layer, with the nitrogen concentration decaying away into theburied oxide layer (as well as decaying into the upper silicon layer).Accordingly, in one embodiment, the etch stop layer 330 may comprisenitrogen-doped silicon dioxide, and in a further embodiment the etchstop layer may comprise silicon oxynitride. In another embodiment, theetch stop layer 330 may comprise a combination of two or more of siliconnitride, nitrogen-doped silicon dioxide, and silicon oxynitride.

Annealing to form the silicon dioxide layer (from the implanted oxygen)and the etch stop layer (from the implanted nitrogen) may be performedunder any suitable conditions which can lead to the formation of silicondioxide and silicon nitride, nitrogen-doped silicon dioxide, or siliconoxynitride (or some combination of these materials). In one embodiment,anneal is performed at a temperature of approximately 1350 degreesCelsius for between approximately 5 to 12 hours. According to anotherembodiment, the wafer is placed in a process chamber in which nitrogenand/or oxygen can be introduced, and annealing is performed in a flowingnitrogen and/or oxygen environment.

Referring to FIG. 8, illustrated is an embodiment of a computer system800. Computer system 800 includes a bus 805 to which various componentsare coupled. Bus 805 is intended to represent a collection of one ormore buses—e.g., a system bus, a Peripheral Component Interface (PCI)bus, a Small Computer System Interface (SCSI) bus, etc.—thatinterconnect the components of system 800. Representation of these busesas a single bus 805 is provided for ease of understanding, and it shouldbe understood that the system 800 is not so limited. Those of ordinaryskill in the art will appreciate that the computer system 800 may haveany suitable bus architecture and may include any number and combinationof buses.

Coupled with bus 805 is a processing device (or devices) 810. Theprocessing device 810 may comprise any suitable processing device orsystem, including a microprocessor, a network processor, an applicationspecific integrated circuit (ASIC), or a field programmable gate array(FPGA), or similar device. It should be understood that, although FIG. 8shows a single processing device 810, the computer system 800 mayinclude two or more processing devices.

Computer system 800 also includes system memory 820 coupled with bus805, the system memory 820 comprising, for example, any suitable typeand number of memories, such as static random access memory (SRAM),dynamic random access memory (DRAM), synchronous DRAM (SDRAM), or doubledata rate DRAM (DDRDRAM). During operation of computer system 800, anoperating system and other applications may be resident in the systemmemory 820.

The computer system 800 may further include a read-only memory (ROM) 830coupled with the bus 805. During operation, the ROM 830 may storetemporary instructions and variables for processing device 810. Thesystem 800 may also include a storage device (or devices) 840 coupledwith the bus 805. The storage device 840 comprises any suitablenon-volatile memory, such as, for example, a hard disk drive. Theoperating system and other programs may be stored in the storage device840. Further, a device 850 for accessing removable storage media (e.g.,a floppy disk drive or a CD ROM drive) may be coupled with bus 805.

The computer system 800 may also include one or more I/O (Input/Output)devices 860 coupled with the bus 805. Common input devices includekeyboards, pointing devices such as a mouse, as well as other data entrydevices, whereas common output devices include video displays, printingdevices, and audio output devices. It will be appreciated that these arebut a few examples of the types of I/O devices that may be coupled withthe computer system 800.

The computer system 800 may further comprise a network interface 870coupled with bus 805. The network interface 870 comprises any suitablehardware, software, or combination of hardware and software that iscapable of coupling the system 800 with a network (e.g., a networkinterface card). The network interface 870 may establish a link with thenetwork (or networks) over any suitable medium—e.g., wireless, copperwire, fiber optic, or a combination thereof—supporting the exchange ofinformation via any suitable protocol—e.g., TCP/IP (Transmission ControlProtocol/Internet Protocol), HTTP (Hyper-Text Transmission Protocol), aswell as others.

It should be understood that the computer system 800 illustrated in FIG.8 is intended to represent an exemplary embodiment of such a system and,further, that this system may include many additional components, whichhave been omitted for clarity and ease of understanding. By way ofexample, the system 800 may include a DMA (direct memory access)controller, a chip set associated with the processing device 810,additional memory (e.g., a cache memory), as well as additional signallines and buses. Also, it should be understood that the computer system800 may not include all of the components shown in FIG. 8.

In one embodiment, the computer system 800 includes a component havingan integrated circuit die that was formed on an SOI wafer having an etchstop layer, such as a silicon nitride layer, as described above. Forexample, the processing device 810 of system 800 may include such anintegrated circuit die. However, it should be understood that othercomponents of system 800 (e.g., network interface 870, etc.) may includea device having an integrated circuit die formed on an SOI waferincluding a silicon nitride etch stop (or other etch stop layer).

The foregoing detailed description and accompanying drawings are onlyillustrative and not restrictive. They have been provided primarily fora clear and comprehensive understanding of the disclosed embodiments andno unnecessary limitations are to be understood therefrom. Numerousadditions, deletions, and modifications to the embodiments describedherein, as well as alternative arrangements, may be devised by thoseskilled in the art without departing from the spirit of the disclosedembodiments and the scope of the appended claims.

1-26. (canceled)
 27. A semiconductor wafer comprising: a base layercomprised of a semiconductor material; a layer of an insulating materialoverlying the base layer; an etch stop layer overlying the insulatinglayer; and an upper layer comprised of the semiconductor materialoverlying the etch stop layer.
 28. The wafer of claim 27, wherein thesemiconductor material comprises silicon and the insulating materialcomprises silicon dioxide.
 29. The wafer of claim 27, wherein the etchstop layer comprises a material selected from a group consisting ofsilicon nitride, nitrogen-doped silicon dioxide, and silicon oxynitride.30. The wafer of claim 27, wherein the etch stop layer comprises atleast two materials selected from a group consisting of silicon nitride,nitrogen-doped silicon dioxide, and silicon oxynitride. 31-40.(canceled)